Non-volatile semiconductor memory devices enjoy widespread use in a variety of applications. In particular, non-volatile devices are especially applicable to portable devices, since such devices are designed to retain data in situations where power is not always available or is frequently interrupted, or where low power usage is required. Such devices include mobile telecommunication systems, memory cards, digital cameras, camcorders, printers, scanners, music players, and the like.
A conventional non-volatile memory device includes an array of individually addressable memory cells at which data can be written to and read from. Reference is made to FIGS. 1A, 1B and 1C, which are a plan view, a cutaway side view taken along section line I-I′ of FIG. 1A, and a circuit diagram, respectively, of a memory cell of a conventional non-volatile memory device.
Referring to FIGS. 1A and 1B, isolation structures 13, for example shallow trench isolation (STI) structures, are formed in a semiconductor substrate 11, defining active regions therebetween at which memory cells can be formed. Referring to FIG. 1C, each memory cell includes two transistors; namely a select transistor ST and a memory transistor MT. A bit line BL extends in a row direction, and a word line WL and sense line SL, extend in a column direction, perpendicular to the row direction. The select transistor ST comprises a select gate 27 that is spaced apart from the upper surface of the substrate 11 by a gate oxide pattern 17. Select gates 27 of memory cells of a common column of the memory cell array are connected by a word line WL. The memory transistor MT comprises a floating gate 21 that is spaced apart from the upper surface of the substrate 11 by a tunnel oxide pattern 15. A control gate 25 is formed on the floating gate 21, spaced apart from the floating gate 21 by a blocking oxide pattern 23. Control gates 25 of memory cells of a common column of the memory cell array are connected by a sense line SL. A source region 12s, a floating junction region 12f, and a drain region 12d are formed in upper surface regions of the substrate 11, by doping the substrate 11 with impurities. An insulation layer 37 is formed on the resulting structure and a bit line BL is provided on the insulation layer 37 to extend in a row direction between neighboring memory cells of a common row of the memory cell array. The bit line BL is connected to the drain regions 12d of the memory cells of a common row by a conductive inter-layer via 31 that extends vertically through the insulation layer 37.
The operation of the memory cell illustrated in FIGS. 1A-1C is well characterized in the field. A program operation is performed by connecting a high voltage to the sense line to cause electrons to be stored in the floating gate 21. The programming of the floating gate 21 is determined according to the status of the bit line BL. A read operation is performed by applying a Vcc voltage to the word line WL and the sense line SL. The resulting potential that is applied to the bit line BL determines whether charge is stored at the floating gate 21, and therefore determines the level of the data applied to the bit line BL. The program and erase operations depend on the well-characterized Fouler-Nodheim (FN) tunneling phenomenon. A FN-tunneling based device generally has superior performance over non-volatile devices that rely on the hot carrier injection phenomenon, since FN devices operate at lower currents, and therefore are better suited for portable devices.
With the continuing trend toward higher integration in semiconductor devices, there is a limit in the amount to which a memory cell can be reduced in size while ensuring effective operation. In the present device, such limitations are present in the feature sizes of the devices, for example, in the gate lengths of the select and memory transistors. Accordingly, further integration of such devices is becoming increasingly difficult as feature sizes approach the atomic scale, and as advances in conventional photolithographic fabrication techniques are less frequent at such reduced feature sizes.